A partitioning programming environment for a novel parallel architecture

Author

Hartenstein, R. ; Becker, J. ; Herz, M. ; Kress, R. ; Nageldinger, U.

Author_Institution

Kaiserslautern Univ., Germany

fYear

1996

fDate

15-19 Apr 1996

Firstpage

544

Lastpage

548

Abstract

The paper presents a partitioning and parallelizing programming environment for a novel parallel architecture. This universal embedded accelerator is based on a reconfigurable datapath hardware. The partitioning and parallelizing programming environment accepts C programs and carries out both a profiling-driven host/accelerator partitioning for performance optimization in a first step, and in a second step a resource-driven sequential/structural partitioning of the accelerator source code to optimize the utilization of its reconfigurable resources

Keywords

optimising compilers; parallel architectures; parallelising compilers; program interpreters; programming environments; reconfigurable architectures; software performance evaluation; software tools; C programs; accelerator partitioning; embedded accelerator; novel parallel architecture; parallelizing compiler; parallelizing programming environment; partitioning programming environment; performance optimization; profiling-driven partitioning; reconfigurable datapath hardware; resource-driven sequential partitioning; resource-driven structural partitioning; Coprocessors; Digital signal processing; Electronic mail; Hardware; Logic arrays; Optimization; Parallel architectures; Parallel processing; Partitioning algorithms; Programming environments;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Processing Symposium, 1996., Proceedings of IPPS '96, The 10th International

Conference_Location

Honolulu, HI

Print_ISBN

0-8186-7255-2

Type

conf

DOI

10.1109/IPPS.1996.508109

Filename

508109