A Low Area Pipelined FFT Processor for OFDM-Based Systems

In this paper, a memory-based architecture of FFT processor customized for OFDM-based communication systems is presented. For the finite word length effects consideration of the decimation in time (DIT) and decimation in frequency (DIF) algorithms, DIF algorithm is selected in our design. Complex multiplication is the main design key in the FFT butterfly transform, a simplification of the complex multiplication is performed by an improved algorithm, and then a pipelined butterfly processing element (BPE) is described accordingly. We also adopt an efficient memory access scheme to achieve considerable power consumption and cost reduction. Finally, a VLSI implementation of radix-2 DIF FFT processor is carried out in a 0.13 mum CMOS technology. The estimated area and power consumption of the proposed FFT processor are 2.96 mm² and 268 mW respectively. The proposed low area pipelined FFT processor is multimode/multistandard and can be suitably applied in WALN, DVB-T, ADSL and the other OFDM-based multicarrier systems.