Design of ternary D flip-flop using one latch with neuron-MOS literal circuit

A new ternary D flip-flop using one latch is presented. In order to meet the non-transparent demand in flip-flops, the narrow pulses produced by the race-hazard of the clock signal are used to control the latch. In the proposed design scheme, literal functions are realized by using neuron-MOS transistors. Then, the pass transistors used to pass ternary signal are controlled by the outputs of the literal circuit to realize ternary inverter and identity cell. As the variable threshold voltage can be achieved easily in neuron-MOS literal circuit, the proposed ternary circuit has simple structure. Compared to the traditional voltage-mode MVL flip-flops, the proposed ternary flip-flop can be fabricated by standard CMOS process with a double-ploy layer, without multi-level ion implantation applied in the conventional voltage-mode multiple-valued circuits. HSPICE simulation results using TSMC 0.35μm double-poly 4-metal CMOS process parameters have verified the characteristics of the proposed scheme. The proposed construction can be easily extended to the design of multiple-valued edge-triggered flip-flop with a higher radix.