Title :
An all-digital Built-In Self-Test for Charge-Pump Phase-Locked Loops
Author :
Lanhua Xia ; Jianhui Wu ; Meng Zhang
Author_Institution :
Nat. ASIC Syst. Eng. Technol. Res. Center, Southeast Univ., Nanjing, China
Abstract :
Mixed-signal testing is becoming an important issue that affects both the time-to-market and product cost of many SoCs. This paper presents an effective Built-in Self-Test (BIST) method of Charge-Pump Phase-Locked Loops (CP-PLL) which is a mixed-signal circuit widely used in most of SoCs. This BIST will use the existing circuits units as test device in the test mode. It can be easily implemented with several logic gates combined with some delay units and the test output is purely digital. The simulation results show higher fault coverage and lower area overhead than that of previous test methods. Thus it provides an efficient structural test which is suitable for a production test.
Keywords :
built-in self test; charge pump circuits; fault simulation; mixed analogue-digital integrated circuits; phase locked loops; production testing; system-on-chip; BIST; CP-PLL; SoC; all-digital built-in self test; area overhead; charge pump phase-locked loops; fault coverage; logic gates; mixed-signal testing; production test; system-on-chip; Built-in self-test; Charge pumps; Circuit faults; Discharges (electric); Phase locked loops; Voltage-controlled oscillators; BIST; CP-PLL; digital testing; mixed-signal testing;
Conference_Titel :
Intelligent Signal Processing (WISP), 2013 IEEE 8th International Symposium on
Conference_Location :
Funchal
Print_ISBN :
978-1-4673-4543-9
DOI :
10.1109/WISP.2013.6657490
