A Low Power Communication Circuit Design Using Selective Glitch Removal Method

In this paper presents a low power communication circuit design using selective glitch removal method. A given Boolean network has to be represented to DAG. The proposed method consists of four steps. In the first step, TD (transition density) calculation has to be performed. Total power consumption is obtained by calculating switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the third step, the glitch removal is processed by a feasible mapping cluster have maximum TD value. In the last step, the CLB packing process. The proposed method is examined by using benchmarks in SIS, it compared power consumption to a CLB-based CPLD low power technology mapping algorithm for trade-off. The experiments results show reduction in the power consumption by 9.67% comparing with that of a CLB-based CPLD low power technology mapping algorithm for trade-off.