DocumentCode :
2135545
Title :
FPGA Low Power Technology Mapping for Reuse Module Design under the Time Constraint
Author :
Kim, Jae-Jin ; Yang, Hyeon-Mi ; Ryu, Keun-Ho ; Kim, Hi-Seok
Volume :
2
fYear :
2008
fDate :
13-15 Dec. 2008
Firstpage :
57
Lastpage :
61
Abstract :
In this paper, FPGA low power technology mapping for reuse module design under the time constraint is proposed. Traditional high-level synthesis does not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using FPGA technology mapping algorithm for selection reuse module by scheduling.
Keywords :
field programmable gate arrays; high level synthesis; low-power electronics; scheduling; FPGA technology mapping; high-level synthesis; low power circuit; multicycling; reuse module design; scheduling task; selection reuse module; time constraint; user-defined datapath component; Adders; Capacitance; Energy consumption; Field programmable gate arrays; High level synthesis; Job shop scheduling; Libraries; Switches; Switching circuits; Time factors; Low Power; Reuse Module Design; Time Constraint;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Future Generation Communication and Networking, 2008. FGCN '08. Second International Conference on
Conference_Location :
Hainan Island
Print_ISBN :
978-0-7695-3431-2
Type :
conf
DOI :
10.1109/FGCN.2008.109
Filename :
4734172
Link To Document :
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