Dynamic programming approach to high frame-rate stereo correspondence: A pipelined architecture implemented on a field programmable gate array

Estimation of depth within an imaged scene can be formulated as a stereo correspondence problem. Typical software solutions tend to be too slow for high frame rate (i.e. ges 30 fps) performance. Equivalent hardware solutions, however, can result in marked improvements. This paper explores one such pipelined hardware implementation that generates dense binocular disparity (depth) estimates at frame rates of up to 200 fps or more. The architecture is based on a dynamic programming maximum likelihood (DPML) formulation developed by Cox et al. [1996]. A field programmable gate array (FPGA) implementation of this architecture demonstrates equivalent accuracy while executing at significantly higher frame rates. It is noted that the architecture holds potential for more generalized hardware implementations of dynamic programming solutions [W. James et al.].