Implementation of a SliM array processor

Presents the design and implementation of a SliM (Sliding Memory plane) array processor, which is a mesh-connected SIMD architecture. To build the array processor, we developed a SliM chip consisting of mesh-connected 5×5 processing elements (PEs). Due to the idea of sliding (i.e. overlapping the inter-PE communication with the computation), the SliM chip can greatly reduce the inter-PE communication overhead, a disadvantage of existing SIMD array processors. This paper addresses architectural and implementation issues of the SliM chip and the SliM array processor. The chip operates at 25 MHz and gives 625 MIPS. We implemented the protype SliM array processor for real-time image processing