Debug port controller architectures for system-on-chip integrated circuits

Since its introduction, test access port has become an inseparable part of the majority of integrated circuits. Commonly referred to as JTAG, it meant to provide a solution to the problem of testing assembled printed circuit boards as well as a means of accessing and controlling on-chip test-dedicated features. With appearance and ever increasing complexity of multi-processor system-on-chip integrated circuits, the architectural variety and intended roles of JTAG based test features significantly expanded. Observability and controllability of an integrated circuitpsilas functionality for debug and test, security protection, power management, clocking schemes management is only a partial list of the features a JTAG based test and debug controller supports in a modern system-on-chip. This paper presents a categorization and analysis of debug port controller architectures and their key features for use in system-on-chip integrated circuits.