Title :
Design of one-vector testable binary systems based on ternary logic
Author_Institution :
Dept. of Comput. Sci. & Eng., Shanghai Tiedao Univ., China
Abstract :
A new concept, one-vector testability, is defined. Design method to achieve one-vector testability of binary systems based on ternary logic is proposed. Some techniques for designing testable binary systems based on ternary circuits are re-examined by using the proposed design method
Keywords :
design for testability; logic design; logic testing; ternary logic; one-vector testability; one-vector testable binary systems; ternary logic; Arc discharges; Circuit faults; Circuit testing; Costs; Design engineering; Design for testability; Logic design; Logic testing; Multivalued logic; System testing;
Conference_Titel :
Multiple-Valued Logic, 1996. Proceedings., 26th International Symposium on
Conference_Location :
Santiago de Compostela
Print_ISBN :
0-8186-7392-3
DOI :
10.1109/ISMVL.1996.508337
