DocumentCode
2136521
Title
Communication optimizations for fine-grained UPC applications
Author
Chen, Wei-Yu ; Iancu, Costin ; Yelick, Katherine
Author_Institution
Lawrence Berkeley Nat. Lab., California Univ., Berkeley, CA, USA
fYear
2005
fDate
17-21 Sept. 2005
Firstpage
267
Lastpage
278
Abstract
Global address space languages like UPC exhibit high performance and portability on a broad class of shared and distributed memory parallel architectures. The most scalable applications use bulk memory copies rather than individual reads and writes to the shared space, but finer-grained sharing can be useful for scenarios such as dynamic load balancing, event signaling, and distributed hash tables. In this paper we present three optimization techniques for global address space programs with fine-grained communication: redundancy elimination, use of split-phase communication, and communication coalescing. Parallel UPC programs are analyzed using static single assignment form and a dataflow graph, which are extended to handle the various shared and private pointer types that are available in UPC. The optimizations also take advantage of UPC´s relaxed memory consistency model, which reduces the need for cross thread analysis. We demonstrate the effectiveness of the analysis and optimizations using several benchmarks, which were chosen to reflect the kinds of finegrained, communication-intensive phases that exist in some larger applications. The optimizations show speedups of up to 70% on three parallel systems, which represent three different types of cluster network technologies.
Keywords
distributed shared memory systems; optimisation; parallel architectures; communication coalescing; communication optimizations; cross thread analysis; dataflow graph; distributed memory parallel architectures; fine-grained UPC applications; fine-grained communication; finer-grained sharing; global address space programs; parallel UPC programs; redundancy elimination; relaxed memory consistency model; shared memory parallel architectures; split-phase communication; static single assignment; Delay; Electronics packaging; Laboratories; Load management; Message passing; Parallel architectures; Program processors; Programming profession; Read-write memory; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Architectures and Compilation Techniques, 2005. PACT 2005. 14th International Conference on
ISSN
1089-795X
Print_ISBN
0-7695-2429-X
Type
conf
DOI
10.1109/PACT.2005.13
Filename
1515599
Link To Document