Title :
On the use of VHDL as a multi-valued logic simulator
Author_Institution :
R. Mil. Coll. of Canada, Kingston, Ont., Canada
Abstract :
This work demonstrates how VHDL can be used as a potential tool for the simulation of multi-valued digital circuits and systems. Although not all features of a given VHDL simulator can be applied to MVL signals, some can easily be adapted to provide enough information to verify functionality and/or timing specifications. The VHDL modelling and simulation of two simple ternary circuits are described and commented
Keywords :
circuit analysis computing; digital circuits; hardware description languages; logic CAD; multivalued logic circuits; VHDL; functionality; multi-valued logic simulator; simulation; ternary circuits; timing specifications; Boolean algebra; Circuit simulation; Context modeling; Displays; Libraries; Logic circuits; Logic functions; Multivalued logic; Packaging; Timing;
Conference_Titel :
Multiple-Valued Logic, 1996. Proceedings., 26th International Symposium on
Conference_Location :
Santiago de Compostela
Print_ISBN :
0-8186-7392-3
DOI :
10.1109/ISMVL.1996.508345
