Title :
A 25 mu m/sup 2/, new poly-Si PMOS load (PPL) SRAM cell having excellent soft error immunity
Author :
Yamanaka, T. ; Hashimoto, T. ; Hashimoto, N. ; Nishida, T. ; Shimuzu, A. ; Ishibashi, K. ; Sakai, Y. ; Shimohigashi, K. ; Takeda, E.
Author_Institution :
Hitachi Ltd., Tokyo, Japan
Abstract :
A 25- mu m/sup 2/ poly-Si PMOS load SRAM (static random access memory) cell, called a PPL cell, has been developed. The cell has been excellent retention characteristics, high soft-error immunity, and low standby power. These advantages are achieved using poly-Si PMOS loads and cross-coupled stacked capacitors formed between the NMOS and the stacked poly-Si PMOS. A large poly-Si PMOS ON current lowers retention voltage to less than 0.5 V and the soft error rate (SER) under high-speed operation by about an order of magnitude. A 5-fF cross-coupled capacitor improves the retention mode SER by more than an order of magnitude and low standby power is attained with a 0.1-pA OFF current of the poly-Si PMOS. The performance has been evaluated using a 4-kbit SRAM. The cell area has been reduced to 25.38 mu m/sup 2/ using half-micron CMOS technology.<>
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; random-access storage; 0.1 pA; 0.5 V; 0.5 micron; 4 kbit; 5 fF; CMOS; PPL cell; SER; SRAM cell; VLSI; cell area; cross-coupled capacitor; cross-coupled stacked capacitors; high-speed operation; low standby power; poly-Si PMOS load SRAM; polycrystalline Si; retention characteristics; retention mode; retention voltage; soft error immunity; soft error rate; static random access memory; CMOS technology; Capacitors; Current supplies; Electrodes; Fabrication; MOSFETs; Random access memory; Resistors; Temperature; Voltage;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32747
