Lowering power consumption using run-time reconfiguration for stereo rectification

Trends of high power usage in portable consumer electronics and high speed designs is an important factor that biases the selection of an ASIC over a FPGA. ASICs are optimized to minimize the amount of logics used for a particular application; reductions in power are noticed when compared against FPGAs design for the same application. On the other hand, some FPGAs equipped with run-time reconfiguration, allow portions of the design to be changed on the fly. Having an appropriate methodology which creates a micro-level static architecture and reduces the reconfiguration overhead is used to lower the power consumption. This can allow the FPGA designs to be somewhat competitive against ASIC designs. This paper explores the reconfiguration methodology to lower the power consumption for the application of stereo rectification. The results obtained show significant savings in logical resources and power consumption when compared to ASIC-like FPGA implementations.