0.5 micron CMOS for high performance at 3.3 V

Author

Chapman, R.A. ; Wei, C.C. ; Bell, D.A. ; Aur, S. ; Brown, G.A. ; Haken, R.A.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

52

Lastpage

55

Abstract

In addition to higher packing density, the scaling of CMOS technology to the half-micron regime must provide improved circuit performance at a reduced supply voltage without increased process complexity. These goals have been met with a 0.5- mu m CMOS technology with 12-nm gate oxide thickness that gives at least a 20% speed improvement at a 3.3-V supply voltage compared to an 0.8- mu m technology at 5.0 V with 20-nm gate oxide. Adequate process margin is obtained by requiring that transistors patterned 0.1 mu m shorter than design length fully meet the requirements for minimum short-channel leakage and sensitivity to hot-carrier stress.<>

Keywords

CMOS integrated circuits; VLSI; digital integrated circuits; integrated circuit technology; 0.5 micron; 12 nm; 3.3 V; CMOS technology; VLSI; gate oxide thickness; packing density; process margin; reduced supply voltage; scaling; sensitivity to hot-carrier stress; short-channel leakage; speed improvement; CMOS technology; Capacitance measurement; Capacitors; Doping; Implants; MOS devices; Process design; Semiconductor diodes; Silicides; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32748

Filename

32748