DocumentCode
2137123
Title
A novel design of low power double edge-triggered flip-flop
Author
Chien-Cheng Yu ; Kuan-Ting Chen
Author_Institution
Dept. of Electron. Eng., Hsiuping Univ. of Sci. & Technol., Taichung, Taiwan
fYear
2012
fDate
16-18 Oct. 2012
Firstpage
1363
Lastpage
1366
Abstract
A double edge-triggered (DET) flip-flop operates on both the rising and falling edges of a clock signal. In this paper, a novel DET flip-flop, suitable for low-power applications, is proposed, Several HSPICE simulations with different input sequences show that the proposed DET flip-flop results in significant power saving as compared to existing DET flip-flops.
Keywords
clocks; flip-flops; logic design; low-power electronics; DET; HSPICE simulations; clock signal; low power double edge-triggered flip-flop; power saving; double edge-triggered (DET); flip-flop; low power consumption;
fLanguage
English
Publisher
ieee
Conference_Titel
Biomedical Engineering and Informatics (BMEI), 2012 5th International Conference on
Conference_Location
Chongqing
Print_ISBN
978-1-4673-1183-0
Type
conf
DOI
10.1109/BMEI.2012.6513131
Filename
6513131
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