Title :
A novel design of low power double edge-triggered flip-flop
Author :
Chien-Cheng Yu ; Kuan-Ting Chen
Author_Institution :
Dept. of Electron. Eng., Hsiuping Univ. of Sci. & Technol., Taichung, Taiwan
Abstract :
A double edge-triggered (DET) flip-flop operates on both the rising and falling edges of a clock signal. In this paper, a novel DET flip-flop, suitable for low-power applications, is proposed, Several HSPICE simulations with different input sequences show that the proposed DET flip-flop results in significant power saving as compared to existing DET flip-flops.
Keywords :
clocks; flip-flops; logic design; low-power electronics; DET; HSPICE simulations; clock signal; low power double edge-triggered flip-flop; power saving; double edge-triggered (DET); flip-flop; low power consumption;
Conference_Titel :
Biomedical Engineering and Informatics (BMEI), 2012 5th International Conference on
Conference_Location :
Chongqing
Print_ISBN :
978-1-4673-1183-0
DOI :
10.1109/BMEI.2012.6513131
