Title :
A modular 1 mu m CMOS single polysilicon EPROM PLD technology
Author :
Cacharelis, P.J. ; Hart, M.J. ; Manley, M.H. ; Frake, S.O. ; Knecht, M.W.
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
Abstract :
The authors describe a single-polysilicon CMOS process that has been optimized for the production of high-speed programmable logic devices (PLDs). The process departs from conventional approaches in two respects: it is a modular addition to a standard CMOS logic process, and it uses a single-polysilicon EPROM cell. The technology has been used to fabricate a 22F10 PLD with an access time of 9.0 ns. Snap-back has been identified as the major cause of program disturb.<>
Keywords :
CMOS integrated circuits; integrated circuit technology; integrated memory circuits; logic arrays; read-only storage; 1 micron; 22F10 PLD; 9 ns; CMOS process; EPROM PLD; EPROM cell; access time; modular addition; program disturb; single polycrystalline Si; snap back; standard CMOS logic process; Auditory implants; CMOS logic circuits; CMOS process; CMOS technology; EPROM; Libraries; Nonvolatile memory; Oxidation; Programmable logic devices; Seals;
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/IEDM.1988.32750
