Architecture of a PDM VLSI fuzzy logic controller with pipelining and optimized chip area

The authors describe the architecture of a fuzzy logic controller using a pulse-width-modulation (PDM) technique and a pipeline structure. Features of this controller are a new architecture for the inference unit, reduced chip area, variable resolution from 1, 2, 3,. . .,254, 255 and fewer input/output (I/O)-pins. Additionally, the architecture has an optimized rule base and its operation time depends only on the resolution. A prototype with two inputs, one output, and a resolution of 8 b has been implemented on field programmable gate arrays (FPGAs) and uses fewer than 10000 gates including internal RAM. A prototype of the controller operates at 6 MHz and needs 170-μs by 8-b resolution or 22-μs by 5-b resolution for one control step, independently of the number of inputs, outputs, and rules