DocumentCode
2138331
Title
Efficient Optimization of H.264 Decoder on PAC Duo SoC Platform
Author
Liu, Kuei-Chun ; Tseng, Shau-Yin ; Wang, Wen-Shan ; Yang, Jen-Kuei ; Su, Wen-Chien
Author_Institution
SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu, Taiwan
fYear
2010
fDate
11-13 Aug. 2010
Firstpage
1
Lastpage
4
Abstract
H.264 has become a popular video compression standard for years; however, the complexity of computation and huge amount of external data access are still the main problems. In this paper, we will propose two mechanisms to fulfill high performance H.264 baseline profile decoder on PAC Duo SOC platform. To reduce the complexity of computation, in addition to algorithm optimization, we use parallelizing method by partitioning the process of the independent data into two processor clusters of PACDSP so that they can be processed in parallel. To reduce the waiting time caused by the latency of external data access, we employ the overlapping approach so that the PACDSP always processes the data without referring to the being transferred external data According to the experimental result of eight baseline CIF sequences, the performance of H.264 decoder software utilizing the mentioned mechanisms is higher than 59.8 frames per second, in average, when runs in one PACDSP in the PAC Duo platform.
Keywords
computational complexity; data compression; decoding; information retrieval; optimisation; parallel processing; video coding; H.264 decoder algorithm optimization; PAC Duo SoC platform; computation complexity; data access; eight baseline CIF sequences; independent data process; parallelizing method; processor clusters; video compression standard; Complexity theory; Decoding; Multimedia communication; Optimization; Software; System-on-a-chip; Video coding;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded and Multimedia Computing (EMC), 2010 5th International Conference on
Conference_Location
Cebu
Print_ISBN
978-1-4244-7710-4
Type
conf
DOI
10.1109/EMC.2010.5575757
Filename
5575757
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