Title :
Asynchronous parallel algorithms for test set partitioned fault simulation
Author :
Krishnaswamy, Dilip ; Banerjee, Prithviraj ; Rudnick, Elizabeth M. ; Patel, Janak H.
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
We propose two new asynchronous parallel algorithms for test set partitioned fault simulation. The algorithms are based on a new two-stage approach to parallelizing fault simulation for sequential VLSI circuits in which the test set is partitioned among the available processors. These algorithms provide the same result as the previous synchronous two stage approach. However, due to the dynamic characteristics of these algorithms and due to the fact that there is very minimal redundant work, they run faster than the previous synchronous approach. A theoretical analysis comparing the various algorithms is also given to provide an insight into these algorithms. The implementations were done in MPI and are therefore portable to many parallel platforms. Results are shown for a shared memory multiprocessor
Keywords :
VLSI; circuit analysis computing; digital simulation; fault diagnosis; integrated circuit testing; logic CAD; message passing; parallel algorithms; sequential circuits; shared memory systems; software portability; synchronisation; MPI; Message Passing Interface; asynchronous parallel algorithms; circuit CAD; dynamic characteristics; redundant work; sequential VLSI circuits; shared memory multiprocessor; software portability; synchronous two stage approach; test set partitioned fault simulation; Algorithm design and analysis; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Distributed computing; Parallel algorithms; Partitioning algorithms; Semiconductor device testing; Sequential circuits;
Conference_Titel :
Parallel and Distributed Simulation, 1997., Proceedings., 11th Workshop on
Conference_Location :
Lockenhaus
Print_ISBN :
0-8186-7964-6
DOI :
10.1109/PADS.1997.594583
