Title :
Fault tolerant XGFT network on chip for multi processor system on chip circuits
Author :
Kariniemi, Heikki ; Nurmi, Jari
Author_Institution :
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
Abstract :
This paper presents a fault-tolerant eXtended Generalized Fat Tree (XGFT) Network-On-Chip (NOC) implemented with a new fault-diagnosis-and-repair (FDAR) system. The FDAR system is able to locate faults and reconfigure switch nodes in such a way that the network can route packets correctly despite the faults. This paper presents how the FDAR finds the faults and reconfigures the switches. Simulation results are used for showing that faulty XGFTs could also achieve good performance, if the FDAR is used. This is possible if deterministic routing is used in faulty parts of the XGFTs and adaptive Turn-Back (TB) routing is used in faultless parts of the network for ensuring good performance and Quality-of-Service (QoS). The XGFT is also equipped with parity bit checks for detecting bit errors from the packets.
Keywords :
error statistics; fault diagnosis; fault tolerance; multiprocessor interconnection networks; network routing; network topology; network-on-chip; quality of service; adaptive turn-back routing; bit errors; deterministic routing; extended generalized fat tree; fault tolerance; fault-diagnosis-and-repair system; multiprocessor system-on-chip circuits; network-on-chip; parity bit checks; quality of service; reconfiguration; route packets; switch nodes; Circuit faults; Computer networks; Fault tolerance; Fault tolerant systems; Logic testing; Network-on-a-chip; Routing; Software testing; Switches; System-on-a-chip;
Conference_Titel :
Field Programmable Logic and Applications, 2005. International Conference on
Print_ISBN :
0-7803-9362-7
DOI :
10.1109/FPL.2005.1515723
