Configurable hardware/software architecture for data acquisition implementation on FPGA

This paper deals with the FPGA-implementation of a configurable hardware/software (HW/SW) architecture for data acquisition (DAQ) systems. The novelty of this paper is to present a HW/SW architecture which can manage most of possible applications in DAQ systems in a very flexible way meeting the performance targets. This architecture can be dynamically reconfigured and therefore adapted depending on the performance of the I/O devices. We implemented and tested our system with three representative applications for large format printers. These three applications differ in terms of sampling frequency, amount of memory and synchronization complexity. The proposed system can also be integrated in an ASIC implementation.