Title :
A multidimensional study on the feasibility of parallel switch-level circuit simulation
Author :
Chen, Yu-an ; Jha, Vikas ; Bagrodia, Rajive
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Abstract :
This paper presents the results of an experimental study to evaluate the effectiveness of multiple synchronization protocols and partitioning algorithms in reducing the execution time of switch-level models of VLSI circuits. Specific contributions of this paper include: parallelizing an existing switch-level simulator such that the model can be executed using conservative and optimistic simulation protocols with minor changes; evaluating effectiveness of several partitioning algorithms for parallel simulation; and demonstrating speedups with both conservative and optimistic simulation protocols for seven circuits, ranging in size from 3 K transistors to about 87 K transistors
Keywords :
VLSI; circuit CAD; circuit analysis computing; digital simulation; integrated circuit design; parallel algorithms; parallel programming; synchronisation; transistor circuits; VLSI circuits; conservative simulation; execution time; experimental study; multidimensional study; multiple synchronization protocols; optimistic simulation protocols; parallel switch-level circuit simulation; partitioning algorithms; speedups; transistors; Circuit simulation; Concurrent computing; Context modeling; Manuals; Multidimensional systems; Protocols; Switches; Switching circuits; Timing; Very large scale integration;
Conference_Titel :
Parallel and Distributed Simulation, 1997., Proceedings., 11th Workshop on
Conference_Location :
Lockenhaus
Print_ISBN :
0-8186-7964-6
DOI :
10.1109/PADS.1997.594585
