An algorithmic study of DDR3 SDRAM on-die termination switch timings

Given the increasing clock signaling rates used by digital memory subsystems, it has become progressively more important that DDR3 SDRAM provide well-controlled impedance to the signal transmission path. The DDR3 specification requires flexible termination, and conformance to analog timing specifications under various operating modes is necessary to ensure reliable system operation. The direct measurement and test of these timings is not possible using simple pass/fail voltage comparators, in the absence of purpose-built hardware (to measure the linear-extrapolated voltage slew rates as defined in the specifications sheet). To get around this limitation, these timing limits are tested in the backend component test flows with two test comparator strobes (per spec) placed at alternative timing and voltage positions. These strobes judge and ensure compliance to MIN and MAX (fastest and slowest) ODT transition timings. The selection of voltage-level and timing-edge offsets requires time-consuming analysis of “shmoo” charts, which are test comparator pass/fail results plotted out across different voltage and timing sweep positions. In this paper, we will share the theory behind an algorithm to visually recognize and extract various signal transition metrics, including slew rates, spec/test points, test-point, and voltage/time offsets from shmoo charts automatically.