Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis

This article describes the theoretical principles and an original microelectronics architecture of a configurable conceptual decoder able to process a MPEG-2 DVB-T stream in real time (T-STD). The proposed hardware architecture allows to continuously measure the quality of service of the MPEG-2 stream component. The architecture has been modelled, validated and simulated by using the SystemC language in combination with real MPEG-2 DVB-T streams. It is composed of several modules allowing to model the various buffers of the T-STD parts (video, audio or system). Real time errors flags are generated when the buffers filling level becomes illegal (overflow, empty buffer, transfer delay). A VHDL model allows an implementation on the FPGA circuit Altera APEX20KE600. The hardware implementation of the configurable T-STD requires 9738 logical cells (LCs) and 12 kB of external memory.