Memory efficient design of an MPEG-4 video encoder for FPGAs

The improving resolutions of new video appliances continuously increase the throughput requirements of video codecs and complicate the challenges encountered during their cost-efficient design. We propose an FPGA implementation of a high-performance MPEG-4 video encoder. The fully dedicated video pipeline is realized using a systematic design approach and exploits the inherent functional parallelism of the compression algorithm. The effect of memory and algorithmic optimizations applied at the high-level are measured on the RTL description. The resulting MPEG-4 video encoder efficiently uses the FPGA blockRAMs, uses burst oriented accesses to external memory and supports real-time processing of 30 4CIF frames per second.