Title :
Architecture-adaptive routability-driven placement for FPGAs
Author :
Sharma, Akshay ; Hauck, Scott ; Ebeling, Carl
Author_Institution :
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
Abstract :
Current FPGA placement algorithms estimate the routability of a placement using architecture-specific metrics. The shortcoming of using architecture-specific routability estimates is limited adaptability. A placement algorithm that is targeted to a class of architecturally similar FPGAs may not be easily adapted to other architectures. The subject of this paper is the development of a routability-driven architecture adaptive FPGA placement algorithm called Independence. The core of the Independence algorithm is a simultaneous place-and-route approach that tightly couples a simulated annealing placement algorithm with an architecture adaptive FPGA router (Pathfinder). The results of our experiments demonstrate Independence´s adaptability to island-style FPGAs, a hierarchical FPGA architecture (HSRA), and a coarse-grained reconfigurable architecture (RaPiD). The quality of the placements produced by Independence is within 1.2% of the quality of VPRs placements. 17% better than the placements produced by HSRA´s placer, and within 0.7% of RaPiD´s placer. Further, our results show that Independence produces clearly superior placements on routing-poor island-style FPGA architectures.
Keywords :
field programmable gate arrays; integrated circuit layout; network routing; reconfigurable architectures; FPGA placement algorithms; HSRA; Independence; Pathfinder; RaPiD; architecture adaptive FPGA router; architecture-specific metrics; coarse-grained reconfigurable architecture; field programmable gate arrays; hierarchical FPGA architecture; routability; routability-driven architecture; simulated annealing placement algorithm; simultaneous place-and-route approach; Computer science; Costs; Field programmable gate arrays; Hardware; Impedance; Logic; Reconfigurable architectures; Routing; Simulated annealing; Wires;
Conference_Titel :
Field Programmable Logic and Applications, 2005. International Conference on
Print_ISBN :
0-7803-9362-7
DOI :
10.1109/FPL.2005.1515759