• DocumentCode
    2139721
  • Title

    Electrical design optimization and characterization in Cell Broadband Engine package

  • Author

    Goto, Yuichi ; Hosomi, Eiichi ; Harvey, Paul M. ; Kawasaki, Kazushige ; Noma, Hirokazu ; Mori, Hiroyuki ; Miura ; Takiguchi, Iwao ; Audet, Jean ; Mandrekar, Rohan ; Nishio, Toshihiko

  • Author_Institution
    Toshiba Semicond. Co., Kanagawa
  • fYear
    0
  • fDate
    0-0 0
  • Abstract
    Cell Broadband Engine is a microprocessor that has very high processing performance and very high speed I/O to communicate with other devices such as system LSI and memory chips. Design optimization with statistical analysis was carried out. DOE matrix was made with dimension of signal traces and dielectric constant of the insulator in the package substrate. After major factors were detected, random sampling was done to make sure that the distribution of characteristic impedance of signal traces is within the specification. Passive characterization was carried out with test vehicle. Insertion loss and characteristic impedance is dependent on both temperature and water absorption. These environmental factors need to be taken into account when the design rule is determined. After design rule is fixed, circuit simulation for whole signal channel was carried out with considering impedance tolerance in both the package and the printed circuit board. DOE matrix was made and analyzed to determine the major factors on mid-frequency and low-frequency noise in power distribution. Inductance of package substrate and decoupling capacitor are the major effect on the mid-frequency noise, and capacitance of on-module and on-PCB affect low frequency noise. The effect of on-chip parameters was also evaluated. Several types of capacitors were characterized to measure their parasitic parameters
  • Keywords
    design of experiments; environmental factors; integrated circuit design; integrated circuit noise; integrated circuit packaging; microprocessor chips; Cell Broadband Engine microprocessor; DOE matrix; characteristic impedance; circuit simulation; decoupling capacitor; design optimization; environmental factors; impedance tolerance; insertion loss; low-frequency noise; mid-frequency noise; on-chip parameters effect; package substrate; parasitic parameters; passive characterization; power distribution; random sampling; signal traces; statistical analysis; Capacitors; Design optimization; Engines; Impedance; Large scale integration; Low-frequency noise; Microprocessors; Packaging; Transmission line matrix methods; US Department of Energy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2006. Proceedings. 56th
  • Conference_Location
    San Diego, CA
  • ISSN
    0569-5503
  • Print_ISBN
    1-4244-0152-6
  • Type

    conf

  • DOI
    10.1109/ECTC.2006.1645647
  • Filename
    1645647