A low-cost scalable pipelined reconfigurable architecture for simulation of digital circuits

This paper presents a cycle-based hardware simulator for digital circuits using FPGA acceleration. The proposed simulator makes use of two reconfiguration layers, which can eliminate the computational cost of FPGA compilation (map, place and route). At compile time, the original circuit is translated into an equivalent pipelined circuit using a set of basic gates. The architecture is highly scalable without requiring multi-FPGA partitioning, and, more interestingly, the equivalent circuit is a virtual circuit which can exceed the size of the hardware platform and still be simulated. The simulator was validated using the ISCAS´85 benchmarks and the results have been compared to two state-of-the-art commercial software simulators. The results show that the proposed architecture can speedup the execution (compilation + simulation) from 3 to 4 orders of magnitude, using a single large FPGA device.