Simultaneous switching noise in FPGA and structure ASIC devices, methodologies for analysis, modeling, and validation

Simultaneous switching noise (SSN) and its behavior have become increasingly important in high-performance FPGA system design featuring hundreds of I/Os transmitting in parallel at low supply voltage standard. In this paper, we present an in-depth study on SSN by analyzing its behavior in three different domains: time, frequency, and noise spectrum. Cross correlation in these three domains reveals two dominant cause mechanisms: frequency dependent PDN impedance and crosstalk from package-PCB breakout region. Each mechanism has its manifestation in time-domain SSN waveform. Furthermore, simulation confirms our postulations made on examination of experimental data and validates the methodology practical to SSN assessment in FPGA applications