A run-time reconfigurable hardware infrastructure for IP-core evaluation and test

In recent years, there has been increasing interest in exploiting the partial and run-time reconfiguration of FPGAs to develop novel computing systems and applications. This paper proposes a generic, reusable FPGA-based test platform that relies on the run-time reconfigurability of the Xilinx Virtex family of FPGAs and allows a number of hardware components such as Intellectual Property (IP) cores to be loaded into the hardware during run-time for testing and evaluation purposes. The platform can be incorporated into a software-based simulation environment, thus allowing software models or testbenches to interact with the hardware modules inside the FPGA in a co-simulation/emulation manner. A case study is also given to demonstrate the practicality and correctness of a proof-of-concept implementation of the proposed platform.