A high performance hardware architecture for an SAD reuse based hierarchical motion estimation algorithm for H.264 video coding

Author

Yalcin, Sinan ; Ates, Hasan F. ; Hamzaoglu, Ilker

Author_Institution

Fac. of Eng. & Natural Sci., Sabanci Univ., Istanbul, Turkey

fYear

2005

fDate

24-26 Aug. 2005

Firstpage

509

Lastpage

514

Abstract

In this paper, we present a high performance and low cost hardware architecture for real-time implementation of an SAD reuse based hierarchical motion estimation algorithm for H.264/MPEG4 Part 10 video coding. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 68 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 27 VGA frames (640 × 480) or 82 CIF frames (352 × 288) per second.

Keywords

field programmable gate arrays; hardware description languages; motion estimation; real-time systems; reconfigurable architectures; video coding; FPGA implementation; H.264 video coding system; SAD reuse; Verilog HDL; Verilog RTL code; Xilinx Virtex II FPGA; hardware architecture; hierarchical motion estimation algorithm; real-time implementation; Costs; Field programmable gate arrays; Hardware design languages; ISO standards; MPEG 4 Standard; Motion estimation; Standards development; Standards organizations; Video coding; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2005. International Conference on

Print_ISBN

0-7803-9362-7

Type

conf

DOI

10.1109/FPL.2005.1515773

Filename

1515773