DocumentCode :
2139995
Title :
A novel 20-100/spl mu/m pitch IC-to-package interconnect and assembly process for Pb-free solder, copper or gold stud bumps
Author :
Tsai, Jui-Yun ; Sundaram, Venky ; Wiedenman, Boyd ; Sun, Yangyang ; Wong, C.P. ; Tummala, Rao
Author_Institution :
Packaging Res. Center, Georgia Inst. of Technol., Atlanta, GA
fYear :
0
fDate :
0-0 0
Abstract :
This paper presents an IC-to-package interconnect and assembly process for ultra fine pitch flip chip with Pb-free solders, copper, nickel or gold stud bumps and other low-standoff interconnects. Current flip-chip technology is capable of 130-150 mum bump pitch and ITRS, iNEMI and other roadmaps identify the need for less than 50-100 mum peripheral pitch flip-chip interconnections in the next few years. Several interconnect methods are being pursued as alternative to current lead-free solders due to concerns with interconnect fatigue reliability as the pitch decreases to 20mum. These include copper posts/pillars, nickel or other nano-structured interconnects, and gold stud bumps. For any of these interconnects, it is anticipated that an underfill material is necessary to handle the CTE mismatch between the IC and the organic substrate. One of major challenges for ultra-fine pitch (20-100 mum) flip-chip attach is the ability to dispense underfill effectively without voids and defects over large ICs with low stand-off height (10-40 mum) interconnects. The need for highly tilled low CTE and high modulus underfill materials to absorb strains in the ultra-fine pitch interconnects places additional demands on underfill processing. The innovative interconnect and assembly process presented here overcomes these challenges and also has the potential to solve the yield problems associated with current no-flow underfill processes. Initial process development was performed using lead-free solder interconnect and details of the assembly process, bonding conditions, and new underfill material is discussed. Based on extensive process parameter optimization, defect-free interconnect assembly with underfill at 100 mum pitch for a 20 mm times 20 mm IC has been demonstrated with excellent solder wetting to the substrate pads. The novel approach in this paper is also applicable to copper, nickel, gold or other types of interconnects and enables the use of underfill materials with optim- - um combination of thermo-mechanical properties
Keywords :
copper; fine-pitch technology; flip-chip devices; gold; integrated circuit interconnections; integrated circuit packaging; nickel; solders; 10 to 40 micron; 20 mm; 20 to 100 micron; Au; CTE mismatch; Cu; IC-to-package interconnect; Ni; assembly process; bonding conditions; defect-free interconnect assembly; fatigue reliability; flip-chip interconnections; gold stud bumps; innovative interconnect; lead-free solder; low-standoff interconnects; nanostructured interconnects; process development; process parameter optimization; solder wetting; thermomechanical properties; ultra fine pitch flip chip; underfill material; underfill processes; yield problems; Assembly; Capacitive sensors; Copper; Environmentally friendly manufacturing techniques; Fatigue; Flip chip; Gold; Lead; Nickel; Organic materials;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2006. Proceedings. 56th
Conference_Location :
San Diego, CA
ISSN :
0569-5503
Print_ISBN :
1-4244-0152-6
Type :
conf
DOI :
10.1109/ECTC.2006.1645657
Filename :
1645657
Link To Document :
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