A 0.5 mu m isolation technology using advanced polysilicon pad LOCOS (APPL)

Author

Nishihara, T. ; Tokunaga, K. ; Kobayashi, K.

Author_Institution

Sony Corp., Kanagawa, Japan

fYear

1988

fDate

11-14 Dec. 1988

Firstpage

100

Lastpage

103

Abstract

A novel, simple LOCOS (local oxidation of silicon) technology has been developed for 0.5- mu m MOS devices. Using the technology, channel-stop implantation and deep-channel implantation are performed simultaneously after field oxidation. These self-aligned implantations eliminate the lateral diffusion of the channel stop impurities, thus suppressing narrow-width effects. Moreover, the body effects is also minimized because of the optimized impurity profile in the channel region.<>

Keywords

CMOS integrated circuits; insulated gate field effect transistors; integrated circuit technology; ion implantation; semiconductor technology; 0.5 micron; APPL; MOS devices; advanced polysilicon pad LOCOS; body effects; channel region; channel-stop implantation; deep-channel implantation; field oxidation; isolation technology; local oxidation of silicon; optimized impurity profile; polycrystalline Si; self-aligned implantations; suppressing narrow-width effects; Atherosclerosis; Boron; Buffer layers; Impurities; Isolation technology; Leakage current; MOS devices; Oxidation; Semiconductor films; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Type

conf

DOI

10.1109/IEDM.1988.32762

Filename

32762