CPU-independent assembler in an FPGA

We describe a system which enables FPGAs to generate machine code for various CPUs, similar to a conventional assembler. Such conversion from intermediate code to a CPU´s native code can be used as the last step in just-in-time compilation for virtual machines like the Java Virtual Machine. The translation system itself and the FPGA logic are independent of the actual target CPU and can be used with both CISC and RISC CPUs. Due to an extended table lookup, the resulting code is very efficient and gains from pre-calculation of selected constants in the FPGA assembler.