DocumentCode
2140100
Title
Analog integrated circuit design of a hypertrellis decoder
Author
Hu, Zong-Qi ; Mow, Wai Ho ; Ki, Wing-Hung
Author_Institution
Dept. of Electr. & Electron. Eng., The Hong Kong Univ. of Sci. & Technol., China
fYear
2003
fDate
27-29 Aug. 2003
Firstpage
552
Lastpage
556
Abstract
The first integrated analog hypertrellis decoder for a nonbinary (5, 4) single check code over Z4 (the integer ring modulo 4) is presented. Computation is performed at 50MHz in cascode current mode for efficient routing, accuracy and speed. Hard decision outputs are generated for efficient testing, while soft outputs are available for accuracy testing. The chip is designed in a 0.5 μm Agilent CMOS n-well process and occupies an area of 3.8 mm2.
Keywords
CMOS analogue integrated circuits; current-mode circuits; decoding; integrated circuit design; parallel algorithms; Agilent CMOS n-well process; accuracy testing; analog integrated circuit design; cascode current mode; hard decision output; hypertrellis decoder; nonbinary single check code; soft output; Analog integrated circuits; Binary codes; CMOS process; Integrated circuit technology; Iterative algorithms; Iterative decoding; Parity check codes; Routing; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Computing, Applications and Technologies, 2003. PDCAT'2003. Proceedings of the Fourth International Conference on
Print_ISBN
0-7803-7840-7
Type
conf
DOI
10.1109/PDCAT.2003.1236363
Filename
1236363
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