Optimization of start-up time and quiescent power consumption of FPGAs

Mass usage of FPGAs instead of ASICs in many embedded applications is often not feasible because of their slow start up time, which is composed of configuration time, time to initialize peripherals and the boot time of the operating system. Another obstacle is their high quiescent power consumption. In this paper we propose a strategy how both problems can be minimized, especially for more complex applications which require a sophisticated operating system and complex peripherals. Our approach uses recent technologies to freeze the FPGA in a defined state, save this slate and write it back at start up. With this approach the classical boot process of the OS can be omitted. For many applications there is no need to provide the system with power when it is not actually in use since it can be restarted within milliseconds. Our first results show that a reduction of start up time by up to two orders of magnitude is possible.