Title :
FPGA implementation of a GF(22M) multiplier for use in pairing based cryptosystems
Author :
Keller, Maurice ; Kerins, Tim ; Marnane, William
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. Coll. Cork, Ireland
Abstract :
In this paper an architecture for GF(24m) multiplication is outlined. It is illustrated how this operation is critical to efficient hardware implementation of the Tale pairing, which itself is the underlying calculation in many new pairing based cryptosystems. Tate pairing calculation times using an FPGA hardware accelerator are estimated based on results from the multiplier architecture.
Keywords :
cryptography; logic design; multiplying circuits; FPGA implementation; GF(22M) multiplier; Tate pairing; hardware accelerator; pairing based cryptosystems; Arithmetic; Clocks; Costs; Elliptic curve cryptography; Elliptic curves; Equations; Field programmable gate arrays; Galois fields; Hamming weight; Hardware;
Conference_Titel :
Field Programmable Logic and Applications, 2005. International Conference on
Print_ISBN :
0-7803-9362-7
DOI :
10.1109/FPL.2005.1515793
