An FPGA network architecture for accelerating 3DES - CBC

Author

Wee, Chin Mun ; Sutton, Peter R. ; Bergmann, Neil W.

Author_Institution

Sch. of Inf. Technol. & Electr. Eng., Queensland Univ., Brisbane, Qld., Australia

fYear

2005

fDate

24-26 Aug. 2005

Firstpage

654

Lastpage

657

Abstract

This paper presents a DES/3DES core that will support cipher block chaining (CBC) and also has a built in keygen that together take up about 10% of the resources in a Xilinx Virtex II 1000-4. The core will achieve up to 200Mbit/s of encryption or decryption. Also presented is a network architecture that will allow these CBC capable 3DES cores to perform their processing in parallel.

Keywords

cryptography; field programmable gate arrays; logic circuits; logic design; parallel processing; DES/3DES core; FPGA network architecture; Xilinx Virtex II 1000-4; cipher block chaining; decryption; encryption; parallel processing; Acceleration; Computer networks; Cryptographic protocols; Cryptography; Data security; Field programmable gate arrays; Information technology; Internet; Pipeline processing; Virtual private networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2005. International Conference on

Print_ISBN

0-7803-9362-7

Type

conf

DOI

10.1109/FPL.2005.1515806

Filename

1515806

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2140874