Coping with uncertainty in FPGA architecture design

The design of FPGA architectures involves optimization of area, delay, power and routability across hundreds of architectural choices (e.g. LUT size, wire length, flexibility and circuit sizing). Since the difficulty of defining and predicting the design space only grows as we approach 65nm and 45nm processes it is necessary to have a better understanding of uncertainty in the architecture definition. In this paper we look at the sources of uncertainty, describe current unpublished methods for encapsulating error and uncertainty in experiments, and propose new methodologies involving ad-hoc, analytic and Monte Carlo simulation techniques to manage these risks in the future.