Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA

In order to address some problems on increasing traffic accidents, many researchers have paid attention to active safety techniques using sophisticated image processing like license number recognition. However, it is enough for warning a driver against danger of collision to measure distance to a licence plate of a preceeding car. This paper proposes a high speed FPGA off-loading engine for detecting the licence plate. A complicated algorithm is written in Handel-C, and parallel processing is explicitly utilized in every level of implementation; an input image is segmented into 16 areas, and each area is processed in parallel by a multiple calculation unit executing pipeline processing and a distributed memory module. A prototype circuit implemented on a general purpose FPGA board achieved 4.16 times performance as software execution on a Pentium-III desktop PC. The highest performance in literature; 100 frames per second; can be achieved even though extra computation time on an embedded processor and communication time with it are considered.