DocumentCode :
2141089
Title :
Quick-Start and XCP on a network processor: Implementation issues and performance evaluation
Author :
Hauger, Simon ; Scharf, Michael ; Kögel, Jochen ; Suriyajan, Chawapong
Author_Institution :
Inst. of Commun. Networks & Comput. Eng., Univ. of Stuttgart, Stuttgart
fYear :
2008
fDate :
15-17 May 2008
Firstpage :
241
Lastpage :
246
Abstract :
The quick-start extension of the transmission control protocol (TCP), as well as the explicit control protocol (XCP), are experimental congestion control schemes that use router feedback to overcome limitations of TCPpsilas standard mechanisms. Both approaches require additional packet processing in every router and therefore raise the question whether, and how, this can be achieved in high-speed routers. This paper studies the realization complexity of the quick-start and XCP router functions on a network processor. We show that in both cases synchronization issues among parallel processing entities have to be considered, and that this affects the router performance. We develop and compare different synchronization mechanisms for highly parallel packet processing. Our prototype implementation on an Intel IXP network processor allows to quantify the impact on throughput and delay caused by the additional packet processing in the fast path. The measurements reveal that quick-start and XCP processing is feasible at multiple Gbit/s line speed, with quick-start being simpler to scale.
Keywords :
microprocessor chips; parallel processing; performance evaluation; synchronisation; telecommunication congestion control; transport protocols; Intel IXP network processor; congestion control; explicit control protocol; high-speed routers; packet processing; parallel processing; performance evaluation; quick-start extension; realization complexity; synchronization; transmission control protocol; Communication networks; Communication standards; Communication system control; Computer networks; Feedback; Field programmable gate arrays; Parallel processing; Protocols; Prototypes; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Switching and Routing, 2008. HSPR 2008. International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-1981-4
Electronic_ISBN :
978-1-4244-1982-1
Type :
conf
DOI :
10.1109/HSPR.2008.4734450
Filename :
4734450
Link To Document :
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