High Efficient Implementation of Image Matching Algorithm

Image matching is an important portion of image processing. The full search matching algorithm based on pixel gray correlation achieves high accuracy, but can hardly be implemented in real time due to mass of calculation. This paper presents the design of a fast image matching system with high precision and processing capacity of images with various sizes. Under the framework of parallel processing, the formula in correlation coefficients matching is improved. A highly paralleled MAC array is carefully designed to maximize the capability of the reconfigurable logical units inside FPGA. Besides, a combination of delay-switch array and asynchronous reset reduces the complexity of parallel array inputs switch. It also enables the support of images with variable sizes. The system is implemented on Altera Stratix II EP2S60F672 platform. The time for correlation calculation to search a 80*80 real-time image in a 512*512 reference image is about 206ms, with a precision no less than 10"5 and a less than 50% consumption of system resources.