DocumentCode
2141311
Title
The future of CMOS scaling - parasitics engineering and device footprint scaling
Author
Wong, H. S Philip ; Wei, Lan ; Deng, Jie
Author_Institution
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
fYear
2008
fDate
20-23 Oct. 2008
Firstpage
21
Lastpage
24
Abstract
We explore options for device scaling beyond the conventional scaling path. We examine the role of the parasitic capacitance for determining the performance of future one-dimensional FETs. We also explore a possible device scaling path that focuses on aggressive scaling of the contacted gate pitch, which provides performance improvements at both the device and circuit level.
Keywords
CMOS integrated circuits; field effect transistors; CMOS scaling; contacted gate pitch; device footprint scaling; one-dimensional FET; parasitic capacitance; parasitics engineering; Capacitive sensors; Carbon nanotubes; Delay; FETs; III-V semiconductor materials; Lattices; Leakage current; Nanoscale devices; Parasitic capacitance; Semiconductor materials;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Conference_Location
Beijing
Print_ISBN
978-1-4244-2185-5
Electronic_ISBN
978-1-4244-2186-2
Type
conf
DOI
10.1109/ICSICT.2008.4734460
Filename
4734460
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