Air spacer MOSFET technology for 20nm node and beyond

Author

Park, Jemin ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

53

Lastpage

56

Abstract

Two types of air spacer technologies are proposed and TCAD simulation is used to construct 20 nm-gate transistor. One is non-SAC (Self Aligned Contact) process with air spacer. It is compared with nitride-spacer and oxide-spacer transistors representing the two extremes of conventional spacer technologies. With 10 nm air spacers, the CMOS inverter delay is reduced by 45% and 30% compared to the nitride-spacer and oxide-spacer technologies respectively. Furthermore, the switching energy (power consumption) is reduced by 46% and 33% respectively. The other is SAC process with air spacer. 3D mixed mode simulation shows that the 35% area benefit can be retained while improving the speed and switching energy by 75% to be 10% better than a non-SAC device.

Keywords

CMOS integrated circuits; MOSFET; invertors; power consumption; technology CAD (electronics); 3D mixed mode simulation; CMOS inverter delay; TCAD simulation; air spacer MOSFET technologies; nitride-spacer transistors; oxide-spacer transistors; self aligned contact; switching energy; Air gaps; CMOS technology; Capacitance; Chemical vapor deposition; Computer simulation; Doping; Etching; MOSFET circuits; Plugs; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734461

Filename

4734461