Title :
Architectural design of a three dimensional FPGA
Author :
Meleis, Waleed M. ; Leeser, Miriam ; Zavracky, Paul ; Vai, Mankuan M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
Abstract :
The design and evaluation of a 3-dimensional FPGA architecture called Rothko are described. Rothko takes advantage of a novel 3-dimensional VLSI circuit technology developed at Northeastern University that is based on transferred circuits with interconnections between layers of circuits. The Rothko 3-D FPGA architecture is based on a sea-of-gates FPGA model first proposed in the Triptych architecture (a 2-D architecture) in which individual cells have the dual functions of routing and logic implementation. Our 3-D VLSI technology allows metal interconnections to be made between cells on different layers so that Rothko is truly 3-D. A very fine-grain interconnection scheme is provided with each cell connected to the one above/below it. In this paper we present the architectural design of this 3-D FPGA. The 3-D technology that supports the Rothko architecture is also described. An example of mapping a combinational multiplier to both the Rothko and Triptych architectures is provided to demonstrate the advantages of Rothko
Keywords :
VLSI; circuit layout CAD; field programmable gate arrays; integrated circuit interconnections; logic CAD; network routing; 3D VLSI circuit technology; Rothko; Triptych architecture; architectural design; combinational multiplier; metal interconnections; sea-of-gates FPGA model; three dimensional FPGA; transferred circuits; very fine-grain interconnection scheme; Application specific integrated circuits; Computer architecture; Field programmable gate arrays; Integrated circuit interconnections; Logic devices; Programmable logic arrays; Propagation delay; Routing; Switches; Very large scale integration;
Conference_Titel :
Advanced Research in VLSI, 1997. Proceedings., Seventeenth Conference on
Conference_Location :
Ann Arbor, MI
Print_ISBN :
0-8186-7913-1
DOI :
10.1109/ARVLSI.1997.634858