Influence of solder microstructure and oxide layers on high frequency electrical losses of WL-CSP Pb-free interconnections

In this paper, results of study of the effects of microstructures and thick surface oxide layers of near eutectic Sn_3.8Ag_0.7Cu solder alloy on high-frequency losses from 500 MHz to 50 GHz are presented. To analyze the high frequency losses in the solder alloy, a new test method was employed. The test modules consisted of lead-free microstrip lines (SnAgCu) mounted on a low-loss liquid crystal (LCP) polymer substrate. The experimental results showed that the colony size or the high dispersion of the Ag₃Sn and Cu₆Sn₅ intermetallics do not have a significant influence on the high frequency losses. On the contrary, the conductor loss increased when thick oxide layer was present on the surface of the solder alloy. A design rule for insertion loss estimation for hot components was also determined. By making use of the theoretical and experimental results on the annealed SnAgCu specimen the correction coefficient value of 1.4 for the conductor loss was obtained. The increase of conductor loss of the WL-CSP interconnections, having a pitch of 500 mum and bump diameters of 300 mum, was calculated to be about 40% higher for differential and single-ended signaling when the thick oxide layers are present