ArchHDL: A New Hardware Description Language for High-Speed Architectural Evaluation

In this paper, we propose ArchHDL as a new language for hardware RTL modeling and high-speed architectural evaluations. ArchHDL enables an RTL modeling based on C++ and is unique because it treats registers as variables and wires as functions using the lambda expression which newly defined in the C++11. The simulation speed with ArchHDL compiled by GCC is faster than the speed with Verilog HDL compiled by iverilog a free Verilog HDL compiler. From the evaluations with realistic and complex hardware description, we show that the simulation speed with ArchHDL is about 18 times faster than the speed with iverilog.