• DocumentCode
    2141769
  • Title

    Testing superscalar processors in functional mode

  • Author

    Singh, Virendra ; Inoue, Michiko ; Saluja, Kewal K. ; Fujiward, H.

  • Author_Institution
    Nara Inst. of Sci. & Technol., Japan
  • fYear
    2005
  • fDate
    24-26 Aug. 2005
  • Firstpage
    747
  • Lastpage
    748
  • Abstract
    This paper presents a methodology for testing a superscalar processor using functional mode of operation for the performance oriented delay faults. The functional mode test issues for superscalar are discussed. A graph based model is developed and used to develop for the generation of test programs.
  • Keywords
    automatic test pattern generation; delays; fault diagnosis; integrated circuit testing; microprocessor chips; functional mode test; graph model; performance oriented delay faults; superscalar processors testing; test programs generation; Automatic testing; Built-in self-test; Cities and towns; Delay; Microprocessors; Out of order; Performance loss; Pipelines; Registers; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications, 2005. International Conference on
  • Print_ISBN
    0-7803-9362-7
  • Type

    conf

  • DOI
    10.1109/FPL.2005.1515837
  • Filename
    1515837
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2141769