SMT and enhanced SPT with recessed SD to improve CMOS device performance

Author

Fang, S. ; Tan, S.S. ; Yuan, J. ; Liang, Q. ; Dyer, T. ; Robinson, R. ; Liu, J. ; Kim, J.J. ; Zuo, B. ; Belyansky, M. ; Yan, J. ; Luo, Z. ; Li, J. ; Wang, Y. ; Greene, B. ; Ng, H. ; Li, Y. ; Shang, H. ; Maciejewski, E. ; Yang, M. ; Divakaruni, R. ; Leoban

Author_Institution

IBM Semicond. Res. & Dev. Center, Hopewell, VA, USA

fYear

2008

fDate

20-23 Oct. 2008

Firstpage

117

Lastpage

120

Abstract

For nFET, mechanism of stress memorization technique (SMT) has been investigated. It showed, for the first time, that SMT effect on nFET improvement is not only from poly gate, but also from Si at extension area. For pFET, a novel low cost technique to improve device performance by enhanced stress proximity technique (eSPT) with Recessed SD (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. 15% improvement in ring delay has been demonstrated with optimized eSPT.

Keywords

CMOS integrated circuits; field effect transistors; semiconductor devices; stress effects; CMOS device performance; nFET; poly gate; recessed SD; ring delay; stress memorization technique; stress proximity technique; Annealing; CMOS technology; Compressive stress; Cost function; Delay; Implants; Research and development; Semiconductor device manufacture; Surface-mount technology; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-2185-5

Electronic_ISBN

978-1-4244-2186-2

Type

conf

DOI

10.1109/ICSICT.2008.4734487

Filename

4734487